1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to an improvement in a sense amplifier for a non-volatile memory device such as a mask ROM (Read Only Memory) and a PROM (Programmable Read Only Memory).
2. Description of the Prior Art
A non-volatile semiconductor memory device has in general such a block constitution as shown in FIG. 5. More specifically, this device comprises a memory cell array 1 including a plurality of memory cells (not shown) arranged in a matrix of rows and columns, a plurality of word lines WL provided correspondingly of the rows of the array 1 and a plurality of digit lines DL provided correspondingly to the columns of the array 1. A set of address signals AD is supplied to and thus held by an address buffer 5. In response thereto, the buffer 5 outputs internal row address signal ADr and an internal column address signal ADc. The row address signal ADr is supplied to a row selector 6 which then selects and energizes one of the word lines WL. On the other hand, the column address ADc is supplied to a column decoder 7 which then commands a column selector 2 to select one of the digit lines DL. Thus, one of the memory cells coupled to the selected word and digit lines is selected and designated. The memory cell thus selected transfers data stored therein to a sense amplifier 3x. Thus, an output data DTo responsive to the data stored in the selected memory cell is read out through an output buffer circuit 4.
Referring to FIG. 6, there are shown in detail respective parts of the memory cell array 1 and the column selector 2 and the sense amplifier 3x. As shown in FIG. 6, each of the cell arrays MC11 to MC22 is composed of a MOS transistor. This transistor stores data "1" by having a first or high threshold value V.sub.TH and data "0" by having a second or low threshold value V.sub.TL that is lower than the first threshold value V.sub.TH.
The column selector 2 includes a plurality of N-channel MOS transistors Q21, Q22, . . . having gates supplied with column selection signals Y1, Y2, . . . from the column decoder 7 and coupled to an input node N2 of the sense amplifier 3x, and the digit lines DL1, DL2, . . . , respectively.
The sense amplifier 3x includes an inverting amplifier IV31 having an input terminal connected to the input mode N2, an N-channel enhancement-mode transistor Q31 having its source connected to the input terminal of the inverting amplifier IV31 and its gate connected to the output terminal of the inverting amplifier IV31, a P-channel transistor Q34 functioning as a load and having its source connected to a power supply line Vcc and its gate and drain connected to the drain of transistor Q31, a reference voltage generator 31x for generating a reference voltage VRx, and a differential amplifier 32 for comparing a voltage at a node N1 indicative of the drain connection of transistors Q31 and Q34 and the reference voltage VRx and outputting the comparison result OUT.
In operation, assume that the low threshold value V.sub.TL of the memory cell transistor is 1 V and the high threshold voltage V.sub.TH thereof is 7 V, for example. The threshold value of each of column selection transistors Q21, Q22, . . . is almost the same as V.sub.TL. Also assume that the address signal AD causes the word line WL1 and digit line DL1 to be selected. The transistor Q21 is thereby rendered conductive by the column selection signal Y1 taking a selective level of 5 V (selection level). The remaining column selection signals (Y2, . . . ) take a non-selection level of 0 V. Thus, the input node N2 of sense amplifier 3x is connected to the digit line PL1.
On the other hand, the word line WL1 is energized to a selection level of 5 V and the remaining word lines (WL2, . . . ) to a non-selection level of 0 V. The memory cell transistor MC11 is thus selected.
If the memory cell MC11 stores data "1" to have the high threshold value, it is maintained to be non-conductive. The digit line DL1 is thereby charged through the transistors Q31 and Q34 up to a logic high level. If, on the other hand, the memory cell MC11 stores data "0" to have the low threshold value, it is rendered conductive, so that the digit line DL1 is discharged to a logic low level. Thus, the voltage on the digit line DL changes according to the data stored in the selected memory cell.
The operation of the sense amplifier 3x will be described below with reference to the waveform diagram of FIG. 7. The selected memory cell that is in the non-conductive state is referred to as an off-bit, whereas the selected memory cell in the conductive state is referred to as an on-bit. Also, the balanced values of voltages obtained at the off-bit selection time and at the on-bit selection time are written as V.sub.N1 (OFF) and V.sub.N1 (ON), if they are obtained at node N1.
Incidentally, it has been stated that a voltage on the selected digit line DL changes according to the data stored in the selected memory cell. It is now assumed that V.sub.N2 =V.sub.DL1, and the changes in the voltages on nodes N2 and N1 will be described with numerical values.
Node N2 is biassed near the logic threshold voltage (about 1.5 V) of inverting amplifier IV31 and, for example, V.sub.N2 (OFF)-1.50 V and V.sub.N2 (ON=1.45 V.
Since the memory cell MC is required to be small to provide a high integration density, the channel width thereof has to be designed to be very narrow, so that the current drive capability thereof must be very small. For example, the current value of the memory cell is about several .mu.A. In contrast, the current value of each of the transistors used in the decoders 6 and 7 and the like is several 10 mA.
As a result, the difference in voltage between V.sub.N2 (OFF) and V.sub.N2 (ON) is only about 50 mA and therefore the following measures are adopted to amplify the amplitude of the CMOS level (5 V for high level and 0 V for low level) quickly:
Inverting amplifier IV31 and transistor Q31 are built with feedback circuits. If, on the one hand, it is now assumed that the memory cell in the selection state is switched from the on-bit to the off-bit, node N2 will go to a logic high level and the output of inverting amplifier IV31 will go to a logic low level. Consequently, node N1 can be quickly charged up to V.sub.N1 (OFF)=4 V by means of transistor Q31 being electrically disconnected.
If, on the other hand, the memory cell in the selection state is switched from the off-bit to the on-bit, node N2 goes to a logic low level and the output of inverting amplifier IV31 goes to a logic high level. Consequently, node N1 can be quickly discharged up to V.sub.N1 (ON)=3.5 V by means of transistor Q31 being electrically connected.
At this point, the voltage difference between V.sub.N1 (OFF) and V.sub.N1 (ON) is amplified to 0.5 V, and further, an amplitude of a CMOS level can also be obtained in the differential amplifier 32 by comparing the voltage at node N1 and reference voltage VRx and amplifying the difference therebetween.
The set values of V.sub.N1 (OFF), V.sub.N1 (ON), and VRx will be described next in reference to the current-voltage characteristic in FIG. 8.
In the figure, I.sub.MC is a current that flows through a memory cell in its selected state, I.sub.Q34 is a current that flows through the load transistor Q34, and V.sub.TP is the threshold value of the transistor Q34. V.sub.TP and V.sub.CC are 1 V and 5 V, respectively. Since a current does not flow through the memory cell when it is in the off-bit selection state, the following equation is obtained: EQU V.sub.N1 (OFF)=V.sub.CC -V.sub.TP ( 1)
From the above equation (1), there is obtained V.sub.N1 (OFF)=5 V-1 V=4 V. On the other hand, since the memory cell current flows when the memory cell is in the on-bit selection state, the voltage, as I.sub.Q34 and I.sub.MC cross each other, becomes V.sub.N1 (ON).
The V.sub.N1 (ON) can be expressed as follows: EQU V.sub.N1 (ON)=V.sub.CC -V.sub.TP -.alpha. (2)
where .alpha. is a value determined by the magnitudes of I.sub.Q34 and I.sub.MC. From the standpoint of design, .alpha. is preferably to be set to about 0.5 V. From equation (2), there is obtained V.sub.N1 (ON)=5 V-1 V-0.5 V=3.5 V.
Also, VR.sub.x is normally set as follows: EQU VR.sub.x =(V.sub.N1 (OFF)+V.sub.N1 (ON))/2 (3)
From equation (3), there is obtained VR.sub.x =(4 V+3.5 V)/2=3.75 V.
The inverting velocity of the sense amplifier will be described next. The inverting velocities (times) at the off-bit selection time and the on-bit selection time are shown as T(OFF) and T(ON), respectively. Each of these times is the time between the time that an address is switched and the time that the sense amplifier output is inverted.
The operation of the conventional semiconductor memory device has been described on the assumption that node N2 is always biased near the logic threshold value of inverting amplifier IV31.
However, in the actual semiconductor memory device, some of the nonselected digit lines balance with the ground potential level. This is because memory cell MC12 selected in the word line WL1 is electrically connected and therefore the nonselected digit line as such DL2 is discharged. Therefore, when switching of the digit lines was performed at the time of the switching of addresses, the voltage at node N2 is dropped to or near to the ground potential level.
The voltage at node N1 follows the voltage drop on node N2. Consequently, the time it takes for node N2 to recover to V.sub.N2 (ON) deteriorates the inverting velocity. This state is shown in the waveform diagram in FIG. 9.
In order to overcome the deterioration in the inverting velocity, there is an example in which the following measures are adopted.
FIG. 10 shows the sense amplifier of a semiconductor storage device (second example) in which the measures for overcoming the deterioration in the inverting velocity have been adopted.
Sense amplifier 3y is different from the sense amplifier 3x shown in FIG. 6 in that a transistor Q35 is provided for use as a precharge transistor. This transistor Q35 has its source connected to the node N1, its gate connected to the output of inverting amplifier IV31, and its drain connected to power supply line V.sub.CC. The threshold value V.sub.TN of transistor Q35 depends upon the so-called back bias effect and thus has a relatively high value of 2.5 V. Therefore, even if the output of inverting amplifier IV31 were 5 V, it would not be electrically connected unless node N1 is less than V.sub.CC -V.sub.TN =2.5 V. In other words, the transistor Q35 can charge node N1 up to 2.5 V when the voltage on node N1 drops at the time of the switching of digit lines. Since the transistor Q35 is larger in current drive capability than the transistor Q34 and can be set to about ten times as large as the transistor Q34, the recovery of node N2 to V.sub.N2 (ON) can be made quickly due to the existance of the transistor Q35.
If the current drive capability of the load transistor Q34 is set to be large, there will arise the question of whether the precharge transistor Q35 is dispensable. However, setting a large current drive capability of the transistor Q34 is not preferable, because the value of .alpha. in equation (2) becomes small and therefore the stability of the operation of differential amplifier 32 is deteriorated.
The advantages of transistor Q35 become more apparent from FIG. 11. Note that, as compared with FIG. 9, in FIG. 11 the voltage drop at node N1 after switching is 3.5 V-2 V=1.5 V and becomes small. This means that the digit line and the node N1 are charged at high speed by the operation of the transistor Q35. Consequently, it follows that T(OFF) has become high-speed. Turning now to FIG. 12, another sense amplifier and accompanying peripheral circuits are shown as a third example of the conventional semiconductor memory device. This sense amplifier 3z is different from the sense amplifier 3x shown in FIG. 6 in that, between node N1 and power supply potential Vcc, there is provided a P-channel transistor Q36 having its gate and drain connected to the node N1 and a precharge control P-channel transistor Q37 having its source connected to power supply line Vcc, its drain connected to the source of transistor Q36 and its gate supplied with a control signal .phi. is input. This signal .phi. is generated by an address transition detection circuit 8 is incorporated into the semiconductor memory device. The address transition detection circuit 8 includes an address transition detection section 81 and a delay circuit 82, and detects a change in the address value of the address signal AD transferred from the address buffer 5 and generates the control signal .phi. that goes to an active level for a specified period. This semiconductor memory device is disclosed, for example, in Japanese Patent Laid-open Publication No. SHO 57-50390.
The operation of the sense amplifier 3z of this device will be described below in conjunction with the waveform shown in FIG. 13.
If it is now assumed that the address is switched and the control signal .phi. goes to the active low level, the transistor Q37 is turned ON to render the precharge transistor Q36 conductive. The transistor Q36 has about ten times as large current drive capability as the transistor Q34 and thus quickly charges the node N1 up to a level of about (V.sub.CC -V.sub.TP) (=4 V) regardless of the storage information of the memory cell in the selected state. The control signal .phi. is thereafter changed to the high level to turn the transistor Q37 OFF. The transistor Q36 is also rendered non-conductive, consequently.
If, the memory cell in the selected stage is an off-bit, the node N1 remains (V.sub.CC -V.sub.TP) (=V.sub.N1 (OFF)). If, on the other hand, the memory cell in the selected state is an on-bit, node N1 is transferred and balanced to (V.sub.CC -V.sub.TP -.alpha.) (=VS.sub.N1 (ON)).
Note that, in FIG. 13, the voltage drop on node N1 after the address is switched is 1 V. (For example, the voltage on node N1 drops from 3.5 V to 2.5 V). That is, this voltage drop is smaller than the voltage drop (1.5 V) at node N1 shown in the second example. This is because the transistor Q36 charges the node N1 more effectively, since the absolute value of the threshold value (1.0 V) of the transistor Q36 is lower than that (2.5 V) of the transistor Q35 (see FIG. 10). The voltage drop at node N2 can also be described in the same way.
Note that the threshold value of the transistor Q35 can be reduced to a small value by changing the manufacturing process thereof in order to cancel the back bias effect. However, in such a case, the threshold values (normally 1 V) of other N-channel enhancement-mode transistors, which constitute the peripheral circuits and are not subjected to a back bias, are also decreased. That is, it is impossible to change only the threshold value of the transistor Q35 without increasing the number of manufacturing steps.
Unless the number of manufacturing steps is increased, the transistor Q35, takes the enhanced threshold value of about 2.5 V. Therefore, the node N1 can be charged quickly up to 2.5 V, which is an intermediate point of the power supply potential, but, after 2.5 V, the node N1 cannot be charged quickly. The second example therefore has the disadvantages that high-speed operation cannot be attained after 2.5 V.
In the third example, since node N1 is precharged by means of P-channel transistor, it can be charged quickly up to a maximum level of 4 V. However, when the stored information of the memory cell is transferred to the differential amplifier 32, the precharge transistor Q37 is required to be non-conductive, the address transition detection circuit 8 is therefore needed to control the level of the control signal .phi.. The number of circuit elements and wiring layers is increased accordingly. The memory capacity is also lowered accordingly. Further, the voltage at the node N1 is charged to such a level that exceeds the reference voltage TRx, so that the number of the inversion operations of the differential amplifier 32 is increased at the on-bit selection time and therefore the amplifier 32 cannot operate with high reliability.